Sequential Logic Study Module
Typical activities include:
- Recognize the operation of S-R latches based on logic gates
- Determine the truth table of an S-R latch
- Diagnose faults in D-type flip-flop circuits
- Determine the operation of a J-K flip-flop from observations
- Diagnose faults in J-K flip-flop circuits
- State the gate connections required for reducing the count of a binary DOWN counter
- Diagnose faults in J-K based counter circuits
Please note that this resource requires access to an Experiment Platform (either a 300-01 or a 300-02).